Many of semiconductor devices having a stacked structure with a plurality of stacked interconnect layers include vias for connecting an interconnection in a certain interconnect layer to an interconnection in a different interconnect layer. Some vias simply connect an upper-layer interconnection and a lower-layer interconnection. Others connect an upper-layer interconnection or a lower-layer interconnection to an intermediate interconnection formed on an intermediate portion of a via. The intermediate portion of the via is a portion between a top surface and a bottom surface thereof.
The via connected to the intermediate interconnection is formed as follows. Before forming the via, a via connection portion is formed at the end portion of the intermediate interconnection to overlap a region where the via is formed. The via connection portion is a portion of the intermediate interconnection for connecting the via. Then, before forming the upper-layer interconnection, a through-hole for embedding the via is formed until the lower-layer interconnection is reached. The through-hole is formed by etching an insulating film using a resist mask having a pattern for the via formed therein until the via connection portion is exposed, and after the via connection portion is exposed, further etching using the via connection portion as a mask. In so doing, the through-hole is formed using a process by which it is easy to etch the insulating film and it is hard to etch an interconnection material. Then, a via material such as tungsten (W) is embedded into the formed through-hole. Finally, the upper-layer interconnection is formed in connection with the top surface of the via, thereby connecting the upper-layer interconnection, the intermediate interconnection, and the lower-layer interconnection via the via.
In this method, however, steps are formed in the via at a connection location with the via connection portion. The via thus thins toward the lower layers. This facilitates misalignment between the via and the lower intermediate interconnection and lower-layer interconnection. As a result, it is hard to ensure sufficient contact area between the via and the lower intermediate interconnection and lower-layer interconnection. When using this method, therefore, a misalignment margin needs to be added to the via and the interconnection to reduce the misalignment between the via and the interconnection. Note that, in this case, a new problem of increased chip area will arise.
As a method for solving the problem of the misalignment between the via and the interconnection, a method is proposed to remove, in the through-hole forming process, the intermediate interconnection at the same time and expose the end portion of the intermediate interconnection on the side surface of the through-hole. In this case, the formed through-hole can be embedded with an interconnection material to connect the via side surface and the intermediate interconnection end portion. This method can contact the via and the intermediate interconnection in self-alignment, thereby facilitating the alignment between the via and the interconnection.
When using this method, however, if it is hard to have a large cross section of the intermediate interconnection, it is also hard to ensure the sufficient contact area between the via and the intermediate interconnection, thereby increasing contact resistance.